1. Field of the Invention
This invention relates to channel stops for isolating semiconductor devices on a single substrate and, more particularly, to channel stops for isolating plural charge transfer devices (CTD) formed on a single semiconductor substrate.
2. Description of the Prior Art
Channel stops for use in semiconductor devices have been on many forms in the prior art. Channel stops are utilized to isolate plural active MOS devices from each other in a single substrate as is well known. Typically, in HgCdTe (MCT) semiconductor devices, such isolation is provided by a metal gate level which is placed in the region above where the channel stop is to be located in the semiconductor material. This metal gate level which is closer to the semiconductor material than the active metal gates, is biased to some potential such that the semiconductor surface directly underneath it will be accumulative or near flat band. Then, when proper voltage is applied on the active gate above that channel stop region, the surface underneath the channel metal level gate or fieldplate is controlled by the field gate voltage and not by the active gate voltage. The voltage on the field plate must be such as to hold the region thereunder either in accumulation or flat band condition to act as a channel stop. In the case of P-type silicon, either the above described method can be used or an implant can be placed in the channel stop region which is a heavy doping of P-type material (acceptoral) so that, when a voltage is placed on the active gate, the region between active devices is heavily doped and has a different turn on voltage than the active regions to provide device isolation. This procedure cannot be used in MCT because it results in tunneling problems.
The channel stop metal is the lowest metal level in the device being formed and in the channel stop region it must be lower level. The first level of metal that the active region sees is the gate metal.
These prior art methods have certain disadvantages. It is apparent that, if a metal level must be used between active devices, then, in turn, this metal level must be covered with an insulating layer prior to formation of the gate metal. This means that there is an increase in insulator thickness above the active region, resulting in lower well capacity and insulator capacitance.
It is also apparent that additional processing steps are required in adding the extra metal and insulator levels, such extra steps also resulting in decreasing semiconductor device yields and adding to processing costs as is well known in the art. It is therefore apparent that removal of the metal in the channel stop region and the processing steps required therefor has advantages in terms of yield and from a device capacity point of view.